Gate resistance can introduce switching losses that can impact the performance of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). As increasing power density leads to smaller features in active cells, the gate resistance becomes more pertinent to device performance. In a conventional semiconductor device, gate contacts and source contacts are formed in metal one (M1) layer in a dual metal structure over a semiconductor substrate. The gate and source contacts in the M1 layer need to be effectively isolated to prevent electrical shorts. As the power density increases, it has become increasing difficult to effectively isolate the gate and source contacts. In addition, the dual metal structure requires wirebonds to make electrical connections to the gate and source contacts. Wire bonding over a dual metal structure using the existing art with raised or even planarized and segregated metal buses risks breaking the isolation between gate and source creating a short.
Thus, there is a need in the art for a low-resistance gate structure that can effectively remove the need for a dual metal structure and enable a more robust structure for wire bonding.